The present invention relates to a transducer interface arrangement including sensor means for measuring a parameter, an analog-to-digital converter and a selectable resistor string, said sensor means having transducer input terminals to which an excitation voltage is applied and sensor output terminals coupled to data input terminals of said converter, said selectable resistor string having an input connected to said transducer input terminals and being adapted to produce an offset voltage derived from said excitation voltage by means of controlled switches included in said selectable resistor string, said offset voltage being applied to said converter, said analog-to-digital converter comprising a sigma-delta modulator including, connected to said data input terminals, the cascade connection of a first switched-capacitor module, a first differential amplifier, a second switched-capacitor module and a second differential amplifier, and further including a third switched-capacitor module with an input at which a reference voltage is applied and with an output connected to an input of said first differential amplifier as well as a fourth switched-capacitor module with an input at which said reference voltage is applied and with an output connected to an input of said second differential amplifier.
Such a transducer interface arrangement is generally known in the art and most of the sensor means, hereafter merely called sensors, are supplied by an excitation voltage and give a differential output voltage. The differential output voltage is proportional to the excitation voltage and is a function of the parameter to be measured, e.g. pressure, temperature, . . . , by the sensor. For most of the sensors the differential output voltage is composed out of an offset voltage and a real differential signal of interest, and this offset voltage can be much higher than the real differential signal. The offset voltage is depending on the manufacturing of the sensor, for a certain type of sensor this value can have a big tolerance, but for one sensor the value is fairly stable: it only has a small variation over temperature.
The measurement is performed by amplifying the signal at the sensor output terminals in a very low noise amplifier, e.g. a chopper stage, preceding the analog-to-digital converter, or A/D converter. The problem with this arrangement is that the input range of the transducer has to cover the complete range of possible offset and real signals. The offset voltage may, as an example, range from xe2x88x9217.5 mV to +17.5 mV, while the real signal is only a fraction of this and may for instance range from 0 mV to 10 mV. In this way, if a signal with an accuracy of 12 bits has to be measured, the 12 bits are needed on the real input signal, i.e. between 0 mV and 10 mV. But since the whole range of offset and real signals has to be covered, the A/D converter needs to have an input range from xe2x88x9217.5 mV (=xe2x88x9217.5 mV+0 mV) to +27.5 mV (=+17.5 mV+10 mV), and thus an accuracy of more than 14 bits.
A possible way of optimizing this arrangement would be to use a first low noise amplifier stage to amplify the small input signal, followed by a second amplifier stage for shifting the signal so that the real signal of interest fits the input range of the A/D converter at the data input terminals thereof. The second amplifier stage is controlled by the selectable resistor string so that it adds the inverse of the offset voltage to the signal at the sensor output terminals. The original offset voltage is thereby almost removed from the signal applied to the data input terminals of the converter and the accuracy of the A/D converter can be reduced to 12 bits again (or a little higher to have some margin). Such an arrangement needs only once a calibration cycle in order to determine the inverse of the offset voltage.
A disadvantage of this solution is that the second active stage adds a temperature dependent offset, adds extra tolerances on the gain, and leads to additional chip area and power consumption.
An object of the present invention is to provide a transducer interface arrangement of the above known type but without adding unnecessary tolerances to the performances of the arrangement, while saving area and power consumption.
According to the invention, this object is achieved due to the fact that said selectable resistor string is further adapted to produce said reference voltage applied to the inputs of said third and fourth switched-capacitor modules, and that said sigma-delta modulator further includes a fifth switched-capacitor module to an input of which said offset voltage is applied and with an output connected to the input terminals of said first differential amplifier.
In this way, the above mentioned second amplifier stage used for shifting the signal is advantageously replaced by the fifth switched capacitor module of which the power consumption is relatively lower, while requiring less area on the chip and avoiding to introduce extra noise and offset.
In more detail, said first, second, third, fourth and fifth switched-capacitor modules have differential input terminals and differential output terminals and comprise capacitors and switches controlled by a clock signal so as to couple said differential input terminals either to said differential output terminals via said capacitors or to a ground reference terminal at a ground reference voltage.
These switched capacitor modules are mainly used to filter possible differences between an analog ground voltage to which the sensor refers and the ground reference voltage to which the above sigma-delta modulator refers. The switches are controlled by the clock signal to avoid clock overlapping between different phases of the clock signal as will be explained later.
Another characteristic feature of the present invention is that said fifth switched-capacitor module is identical to said first switched-capacitor module.
By duplicating the first switched-capacitor module, that is an input circuitry of the converter, into the fifth switched-capacitor module, an extra input to the converter is provided. A compensation signal for the offset voltage to be eliminated may then be applied to this extra input and so further to the other circuitry of the A/D converter via the fifth switched-capacitor module.
Again in more detail, said fifth switched-capacitor module comprises a first set and a second set of switches, the switches of said first and said second set being respectively closed during a first phase and a second phase of said clock signal, the switches of said first set interconnect a first of the differential input terminals to said ground reference terminal via a first capacitor, and interconnect a second of said differential input terminals to said ground reference terminal via a second capacitor, and the switches of said second set interconnect said second input terminal to a first of the differential output terminals via said first capacitor, and interconnect said first input terminal to a second of said differential output terminals via said second capacitor.
When the switches of the fifth switched-capacitor module are clocked the same way as the switches of the first switched-capacitor module, then a conversion of the sum of the signals at the data input terminals and at the input of the fifth switched-capacitor module is performed by the transducer.
In a variant of this embodiment, said fifth switched-capacitor module comprises a first set and a second set of switches, the switches of said first and said second set being respectively closed during a first phase and a second phase of said clock signal, the switches of said first set interconnect a first of the differential input terminals to said ground reference terminal via a second capacitor, and interconnect a second of said differential input terminals to said ground reference terminal via a first capacitor, and the switches of said second set interconnect said first input terminal to a first of the differential output terminals via said first capacitor, and interconnect said second input terminal to a second of said differential output terminals via said second capacitor.
By changing the clocking of the switches of the fifth switched-capacitor module with respect to those of the first switched-capacitor module, the input signal of the fifth switched-capacitor module is subtracted from the signal at the data input terminals. Then a conversion of the difference of these signals is performed by the transducer rather than the sum thereof.
Referring again to the first embodiment, also another characteristic feature of the present invention is that said first set of switches comprises
a first switch connected between said first input terminal and a first end of said first capacitor,
a second switch connected between a second end of said first capacitor and said ground reference terminal,
a third switch connected between said second input terminal and a first end of said second capacitor, and
a fourth switch connected between a second end of said second capacitor and said ground reference terminal,
and that said second set of switches comprises
a first switch connected between said second input terminal and a first end of said first capacitor,
a second switch connected between a second end of said first capacitor and said first output terminal,
a third switch connected between said first input terminal and a first end of said second capacitor, and
a fourth switch connected between a second end of said second capacitor and said second output terminal.
This relatively simple fifth switched capacitor module requires less chip area and power consumption than the above mentioned second amplifier stage used for shifting the signal that it advantageously replaces.
Still another characteristic feature of the present invention is that said selectable resistor string comprises a plurality of resistors connected in series across the transducer input terminals, that said controlled switches of said selectable resistor string are connected to junction points of the series connected resistors, that said reference voltage is provided at a first reference terminal of said selectable resistor string, connected to a junction point of two series connected resistors, and at a second reference terminal of said selectable resistor string, connected to an end of the series connected resistors, and that said offset voltage is provided at a first offset terminal of said selectable resistor string, connected to a junction point of two series connected resistors via one of said controlled switches, and at a second offset terminal connected to said end of the series connected resistors.
In this way, the same series connected resistors are used to provide both the reference voltage and the offset voltage. The chip area and the power consumption are thus not affected by this improvement.
Additionally to the offset correction, gain setting is also done in a conventional circuit by adding an additional amplifier stage in front of the A/D converter, with all the consecutive drawbacks as explained above.
Therefore, another object of the present invention is to provide a transducer that, additionally to the above-mentioned offset correction, also includes an easy gain setting without dramatically increasing the required chip area and power consumption.
According to the invention, this other object is achieved due to the fact that said first switched-capacitor module has differential input terminals connected to said data input terminals and comprises a first set and a second set of switches, the switches of said first and said second set being respectively closed during a first phase and a second phase of said clock signal, that the switches of said first set interconnect a first of the differential input terminals to said ground reference terminal via a first capacitor, and interconnect a second of said differential input terminals to said ground reference terminal via a second capacitor, that the switches of said second set interconnect said second input terminal to a first of the differential output terminals via said first capacitor, and interconnect said first input terminal to a second of said differential output terminals via said second capacitor, and that said first and said second capacitor are each coupled in parallel with a gain setting module comprising at least one series connection of an extra capacitor and a controlled extra switch.
By adding one or more extra capacitors in parallel with the existing first and second capacitors in the first switched-capacitor module the gain, or input range, of the sigma-delta modulator can be changed. These extra capacitors are selected by the extra switches controlled, e.g., by a digital circuit. These controlled extra switches are not clocked but are switched on or off depending on the desired gain. The more extra capacitors added, the higher the gain.
Further characteristic features of the present transducer interface arrangement are mentioned in the appended claims.